
PIC18F1230/1330
2009 Microchip Technology Inc.
DS39758D-page 145
TABLE 14-6:
REGISTERS ASSOCIATED WITH THE POWER CONTROL PWM MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
IPR3
—
—PTIP
—
PIE3
—
—PTIE
—
PIR3
—
—PTIF
—
PTCON0
PTOPS3
PTOPS2
PTOPS1
PTOPS0
PTCKPS1 PTCKPS
0
PTMOD1 PTMOD0
PTCON1
PTEN
PTDIR
—
PTMRL(1)
PWM Time Base Register (lower 8 bits)
PTMRH(1)
—
PWM Time Base Register (upper 4 bits)
PTPERL(1)
PWM Time Base Period Register (lower 8 bits)
PTPERH(1)
—
PWM Time Base Period Register
(upper 4 bits)
SEVTCMPL(1) PWM Special Event Compare Register (lower 8 bits)
SEVTCMPH(1)
—
PWM Special Event Compare Register
(upper 4 bits)
PWMCON0
—
PWMEN2(2) PWMEN1(2) PWMEN0(2)
—
PMOD2
PMOD1
PMOD0
PWMCON1
SEVOPS3 SEVOPS2
SEVOPS1
SEVOPS0 SEVTDIR
—
UDIS
OSYNC
DTCON
DTPS1
DTPS0
DT5
DT4
DT3
DT2
DT1
DT0
FLTCONFIG
BRFEN
—
FLTAS
FLTAMOD FLTAEN
OVDCOND
—
POVD5
POVD4
POVD3
POVD2
POVD1
POVD0
OVDCONS
—
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
PDC0L(1)
PWM Duty Cycle #0L Register (lower 8 bits)
PDC0H(1)
—
PWM Duty Cycle #0H Register (upper 6 bits)
PDC1L(1)
PWM Duty Cycle #1L Register (lower 8 bits)
PDC1H(1)
—
PWM Duty Cycle #1H Register (upper 6 bits)
PDC2L(1)
PWM Duty Cycle #2L Register (lower 8 bits)
PDC2H(1)
—
PWM Duty Cycle #2H Register (upper 6 bits)
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used with the Power Control PWM.
Note 1:
Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to.
2:
Reset condition of PWMEN bits depends on the PWMPIN Configuration bit.